What should be taken into account when designing high-level HDI boards? How to consider the stack-up structure and signal stability?

The design of high-level HDI boards cannot merely focus on whether the connections can be made; it is also crucial to consider whether the subsequent processing, mass production, and long-term reliable operation can be achieved stably. Especially in fields such as mobile phones, automotive electronics, medical equipment, communication modules, and high-speed computing devices, high-level HDI boards often carry high-density chips, high-speed signals, and multiple power supply systems. Any slight oversight during the design stage may lead to problems such as impedance abnormalities, insufficient hole reliability, layer misalignment, and increased crosstalk in the later stages.

First, clearly define the product positioning to avoid excessive design.

Before designing a high-level HDI board, it is necessary to first determine whether the product truly requires a high-level HDI.

If it is just an ordinary control board, a simple power board or a low-speed signal board, an ordinary multilayer PCB might be sufficient. For the following situations, high-end HDI is more suitable:

Require small-sized and high-density wiring;

The chip is packaged with high-pin BGA technology.

The internal space is limited, so the board area needs to be reduced.

There are requirements for high-speed signals, radio frequency signals or high reliability.

The product has strict requirements for weight, thickness and stability.

The higher the design level, the higher the cost and the greater the processing difficulty. Therefore, one should choose a first-level, second-level, third-level or any level of HDI structure based on the actual functional requirements, rather than blindly pursuing higher specifications.

II. The layered structure should be considered from the perspectives of signal, power supply, and processing.

The laminated structure is the foundation of high-order HDI design. If the laminations are not reasonable, no matter how the wiring is optimized later, it is difficult to ensure stable signals.

When designing the layers, three key points should be given priority consideration.

First, a complete reference plane must be provided for the high-speed signals. The high-speed lines should ideally be placed closely adjacent to a complete plane to minimize interruptions in the return path and reduce the risks of crosstalk and radiation.

Second, it is necessary to properly arrange the power layer and the ground layer. The power layer is adjacent to the ground layer, which helps to form a planar capacitor and improve the power integrity.

Thirdly, the manufacturability of lamination needs to be considered. High-level HDI involves multiple lamination processes, and factors such as the number of layers, dielectric thickness, copper thickness, and material coefficient of thermal expansion all affect the alignment between layers and the control of warpage.

The common design approach is: The high-speed signal layer is placed as close as possible to the ground layer. The power layer is arranged in pairs with the ground layer. The outer layer is used for component connections and short-distance routing, while the inner layer is used for high-speed lines and critical power distribution.

III. The design of micropores should take into account both the wiring density and reliability.

High-level HDI boards commonly use laser micro-holes to achieve inter-layer interconnection. Although the micro-holes save space, the more of them there are and the more complex the structure is, the higher the manufacturing risk becomes.

When designing, the following points should be taken into consideration:

The pore size should not be too small and should be in line with the manufacturer's production capacity.

The size of the solder pads should allow for machining tolerance.

Avoid unnecessary consecutive stacking of holes;

The double-hole structure needs to consider the reliability of filling the holes.

Blind holes, embedded holes and through holes should be assigned to different personnel for separate operations.

If the product reliability is of high importance, it is recommended to preferentially adopt the verified hole structure and avoid overstacking just to save area. For scenarios such as automotive electronics and medical equipment, the reliability of copper in the holes is often more crucial than the maximum density.

Four. BGA fan-out is a key aspect of high-level HDI design.

High-level HDI boards are often designed to address the problem of excessive pin count in BGA chips.

When designing the BGA area, the following aspects should be given priority attention:

Chip ball pitch;

Available wiring channels;

Power ground pin distribution;

Key high-speed signal position

Does the microporous structure adopt the design of holes in the center of the plate?

For small pitch BGA, the conventional through-hole routing is difficult to meet the requirements. Usually, laser blind holes, through-hole in the PCB, filling hole electroplating and other processes need to be combined. During the design process, not only should the automatic routing function of the EDA software be used, but also the minimum hole diameter, minimum pad size, and minimum line width and spacing capabilities of the PCB factory should be taken into account for evaluation.

V. The line accuracy should allow for sufficient manufacturing margins.

High-end HDI boards often require fine-line and fine-pitch designs, but the design parameters cannot be pushed to the limit of the manufacturer's capabilities.

For instance, when the manufacturer claims it can achieve 2mil/2mil, this does not mean that every project is suitable for long-term production at the maximum capacity. For mass production designs, it is more advisable to leave a safety margin.

The following aspects need to be strictly controlled:

Minimum line width

Minimum line spacing

Copper thickness and etching compensation;

Impedance line width

Differential line spacing

Pad-to-line spacing.

The thinner the line, the higher the requirements for exposure, etching, electroplating and AOI inspection. During the design stage, appropriately relaxing the line width and spacing can significantly improve yield and reduce costs.

Six. For high-speed signals, pay attention to the complete return path.

Signal stability is not determined solely by whether the lines are connected; rather, it depends on the complete path of the signal from the sending end to the receiving end.

High-speed signal design should pay attention to:

The wiring should be as short and straight as possible.

Reduce unnecessary vias;

The differential lines maintain the same length and spacing.

Avoid crossing the divided planes;

Controllability of impedance continuity;

Stay away from areas with strong noise power sources;

Keep sufficient space beside the critical line.

If the high-speed line needs to be relocated, ground vias should be placed near the relocation area to provide a continuous path for the return current, thereby reducing signal reflection and electromagnetic interference.

VII. Power integrity cannot be ignored

Many problems with high-end HDI boards are not caused by the signal lines themselves, but by power noise.

When designing, it is necessary to make reasonable planning:

Power layer area;

Plane ground integrity

Decoupling capacitor position

High current path

Number of power via holes;

Length of the chip power supply circuit.

The decoupling capacitor should be placed as close as possible to the chip's power pin, and the connection path should be as short as possible. For high-power chips, it is necessary to avoid a narrow power path that causes excessive voltage drop, while also paying attention to heat dissipation and the carrying capacity of the copper sheet.

VIII. The impedance control must be confirmed with the manufacturer in advance.

High-level HDI boards are commonly used in high-speed communication scenarios, and impedance control is extremely crucial.

Before designing, it is necessary to confirm with the PCB manufacturer:

Panel model;

Medium thickness;

Copper thickness;

Impedance target value

Impedance tolerance;

Processable line width and line spacing.

Do not have the manufacturer reverse the layer stacking after the design is completed. Otherwise, problems such as inability to process the line width, non-compliance with impedance standards, or a significant increase in cost may occur.

IX. Thermal design and mechanical reliability should also be considered simultaneously.

High-level HDI boards have a high device density and the heat is more concentrated.

Please note:

Add thermal conduction channels beneath the high-power chips;

Applying copper evenly helps dissipate heat;

Avoid concentrating heat in a localized area;

Control board thickness and warpage;

Be aware of the impact of welding thermal shock.

For automotive electronics, industrial control systems and medical equipment, the products may operate in complex environments for a long time. Therefore, attention should also be paid to thermal cycling, vibration, humidity and long-term conduction reliability.

10. DFM review should be conducted in the early stage of design.

Modifying the design of high-level HDI boards after they have been completed is very costly. A more reasonable approach is to involve the PCB manufacturer in the DFM review during the initial design stage.

Key checks:

Is the laminated structure capable of being bonded?

Is the microporous structure reliable?

Is the line width and spacing suitable for mass production?

Is the impedance controllable?

Is the BGA fanout reasonable?

Does the surface treatment match the packaging?

Are the test points sufficient?

Is the cost acceptable?